This invention pertains to amplifier circuits suitable for fabrication in CMOS-type technology, and wherein such amplifiers use both bipolar and field-effect transistors.
It is desirable to combine complementary symmetry metal-oxide-semiconductor (CMOS) and bipolar technology using the relatively simple CMOS process to fabricate both MOS transistors an bipolar transistors on the same semiconductor substrate. Such combination offers several important advantages.
One advantage in combining CMOS and bipolar technology is the ability to use both MOS transistors and bipolar transistors together in a linear amplifier to obtain the benefits of the best characteristics of each type of transistor. For example, MOS transistors can provide exceptionally high input impedance, while bipolar transistors can provide much higher current capability than MOS transistors for a given substrate area. Therefore, by using a matched pair of MOS transistors arranged as a differential amplifier input means to provide improved input characteristics, and by using bipolar transistors arranged in current mirror amplifier configurations to provide high performance linear signal gain, the performance level of an operational amplifier circuit using both types of transistors can be improved beyond that available by using MOS or bipolar transistors alone.
Another advantage of combining CMOS and bipolar technology is that digital functions may be advantageously combined with linear functions on the same substrate. For example, the operational amplifier portion of an analog-to-digital converter may be constructed using MOS and bipolar transistors, while the digital control section thereof may be constructed using CMOS transistors as logic elements. Such mixed linear and digital capability leads to still higher levels of integration and more flexible system partitioning between large scale integrated chips.
There are other mixed-technology integrated circuits using FET and bipolar transistors. One such type is a combination of bipolar and junction FET (BiFET). Another type is bipolar and MOS (BiMOS). But BiFET has no suitable logic family, and BiMOS has poor linear packing density. The combination of CMOS and bipolar technology, however, provides both a suitable logic family and improved packing density. Digital logic is provided by conventional CMOS logic circuits. Furthermore, linear packing density is improved by using conventional CMOS guard band techniques to isolate various transistors from each other, to avoid having to devote substantial areas of the chip for the isolation function, as is required in BiMOS technology. Finally, the CMOS fabrication process is generally less complex than either the BiFET or BiMOS processes.